# Atmel EDBG-based Tools Protocols
GET

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#### SET/GET parameters

Table 98. AVR8 SET/GET parameters

Context | ID | Description / values | Access | Size
--- | --- | --- | --- | ---
AVR8_CTXT_CONFIG | AVR8_CONFIG_VARIANT | AVR8_VARIANT_LOOPBACK AVR8_VARIANT_TINYOCD AVR8_VARIANT_MEGAOCD AVR8_VARIANT_XMEGA AVR8_VARIANT_NONE | W | 1 byte
AVR8_CONFIG_FUNCTION | AVR8_FUNC_NONE AVR8_FUNC_PROGRAMMING AVR8_FUNC_DEBUGGING | W | 1 byte
AVR8_CTXT_PHYSICAL | AVR8_PHY_PHYSICAL | AVR8_PHY_INTF_NONE AVR8_PHY_INTF_JTAG AVR8_PHY_INTF_DW AVR8_PHY_INTF_PDI | W | 1 byte
AVR8_PHY_JTAG_DAISY | Devices before << 24 Devices after << 16 IR-bits before << 8 IR-bits after << 0 Note that daisy chain settings must be written before activating the JTAG physical. | RW | 4 bytes
AVR8_PHY_DW_CLK_DIV | debugWIRE clock division factor | W | 1 byte
AVR8_PHY_MEGA_PRG_CLK | JTAG clock frequency (kHz) for programming megaAVR Note: this frequency is limited by the target silicon itself | W | 2 bytes
AVR8_PHY_MEGA_DBG_CLK | JTAG clock frequency (kHz) for debugging megaAVR Note: this frequency must be less than a quarter of the active target clock | W | 2 bytes
AVR8_PHY_XM_JTAG_CLK | JTAG clock frequency (kHz) for programming and debugging AVR XMEGA Note: this frequency is limited by the target silicon itself | W | 2 bytes
AVR8_PHY_XM_PDI_CLK | PDI clock frequency (kHz) for programming and debugging AVR XMEGA Note: this frequency is limited by the target silicon itself | W | 2 bytes
AVR8_CTXT_DEVICE |  | see tables below for family specific contexts | W |
AVR8_CTXT_OPTIONS | AVR8_OPT_RUN_TIMERS | Run timers in stopped mode. This option allows timers to continue to run even when the device has entered stopped mode. This is especially useful for maintaining PWM output values for example in motor control applications. Note that timer interrupts will NOT be serviced until RUN mode is entered. (Not available in AVR XMEGA) | W | 1 byte
AVR8_OPT_DISABLE_DBP | Disables data breaks when resetting. Used internally to prevent variable initialisation routines from triggerring data breakpoints. | W | 1 byte
AVR8_OPT_ENABLE_IDR | Enables messages from the target core. IDR messages can be sent from some target types by writing to the OCD data register during RUN mode. When this option is enabled, these data values will be routed to USB EVENT messages. | W | 1byte
AVR8_OPT_POLL_INT | Adjusts how often the debugger polls the target's state. Value given as polling interval in ms. Possible values: 1, 5, 10, 20, 50 and 100. | W | 1byte
AVR8_CTXT_SESSION | AVR8_SESS_MAIN_PC (deprecated) | Program counter value [word address] of main() function | W | 4 bytes
AVR8_CTXT_TEST | AVR8_TEST_TGT_RUNNING | Actively polls the targets RUN/STOP state. 0x00 = STOPPED 0x01 = RUNNING | R | 1 byte

##### Device context: debugWIRE targets

Table 99. Device context: debugWIRE targets

Addr | Name | Description | Size
--- | --- | --- | ---
0x00 | FLASH_PAGE_BYTES | Flash page size (bytes) | 2 bytes
0x02 | FLASH_BYTES | Flash size (bytes) | 4 bytes
0x06 | FLASH_BASE | Base address of flash | 4 bytes
0x0A | BOOT_SECTION_START | Start address of boot section | 4 bytes
0x0E | SRAM_START | Start address of SRAM | 2 bytes
0x10 | EEPROM_SIZE | EEPROM size (bytes) | 2 bytes
0x12 | EEPROM_PAGE_SIZE | EEPROM page size (bytes) | 1 byte
0x13 | OCD_REV | OCD revision | 1 byte
0x18 | OCDR_ADDR | OCDR address | 1 byte
0x19 | EEARH_ADDR | EEARH address (or EEAR address if only one byte EEAR register) | 1 byte
0x1A | EEARL_ADDR | EEARL address (or EEAR address if only one byte EEAR register) | 1 byte
0x1B | EECR_ADDR | EECR address | 1 byte
0x1C | EEDR_ADDR | EEDR address | 1 byte
0x1D | SPMCR_ADDR | SPMCR address | 1 byte
0x1E | OSCCAL_ADDR | OSCCAL address | 1 byte

##### Device context: megaAVR JTAG targets

Table 100. Device context: Mega targets

Addr | Name | Description | Size
--- | --- | --- | ---
0x00 | FLASH_PAGE_BYTES | Flash page size (bytes) | 2 bytes
0x02 | FLASH_BYTES | Flash size (bytes) | 4 bytes
0x06 | FLASH_BASE | Base address of flash (word address) | 4 bytes
0x0A | BOOT_SECTION_START | Start address of boot section (word address) | 4 bytes
0x0E | SRAM_START | Start address of SRAM (byte address) | 2 bytes
0x10 | EEPROM_SIZE | EEPROM size (bytes) | 2 bytes
0x12 | EEPROM_PAGE_SIZE | EEPROM page size (bytes) | 1 byte
0x13 | OCD_REV | OCD revision | 1 byte
0x18 | OCDR_ADDR | OCDR address | 1 byte
0x19 | EEARH_ADDR | EEARH address (or EEAR address if only one byte EEAR register) | 1 byte
0x1A | EEARL_ADDR | EEARL address (or EEAR address if only one byte EEAR register) | 1 byte
0x1B | EECR_ADDR | EECR address | 1 byte
0x1C | EEDR_ADDR | EEDR address | 1 byte
0x1D | SPMCR_ADDR | SPMCR address | 1 byte
0x1E | OSCCAL_ADDR | OSCCAL address | 1 byte

##### Device context: AVR XMEGA targets

Table 101. Device context: XMEGA targets

Addr | Name | Description | Size
--- | --- | --- | ---
0x00 | APPL_BASE_ADDR | PDI offset for application part of flash (byte address) | 4 bytes
0x04 | BOOT_BASE_ADDR | PDI offset for boot part of flash (byte address) | 4 bytes
0x08 | EEPROM_BASE_ADDR | PDI offset for EEPROM (byte address) | 4 bytes
0x0C | FUSE_BASE_ADDR | PDI offset for fuses (byte address) | 4 bytes
0x10 | LOCKBIT_BASE_ADDR | PDI offset for lock bits (byte address) | 4 bytes
0x14 | USER_SIGN_BASE_ADDR | PDI offset for user signature (byte address) | 4 bytes
0x18 | PROD_SIGN_BASE_ADDR | PDI offset for production signature (byte address) | 4 bytes
0x1C | DATA_BASE_ADDR | PDI offset for SRAM (byte address) | 4 bytes
0x20 | APPLICATION _BYTES | Application section size (bytes) | 4 bytes
0x24 | BOOT_BYTES | Boot section size (bytes) | 2 bytes
0x26 | FLASH_PAGE_BYTES | Flash page size (bytes) | 2 bytes
0x28 | EEPROM_SIZE | EEPROM size (bytes) | 2 bytes
0x2A | EEPROM_PAGE_SIZE | EEPROM page size (bytes) | 1 byte
0x2B | NVM_BASE | NVM controller module base address | 2 bytes
0x2D | SIGNATURE_OFFSET | PDI offset for signature (byte address) | 2 bytes

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